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chriz74
Registered: Apr 2009
Posts: 33 |
What is going on with those ghost bytes in the Ghost demo?
Can anyone explain what’s the catch? |
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Oswald
Registered: Apr 2002
Posts: 5031 |
Quote: "read from precharged address byte" :)
dont think its precharged in c64 if address line or data line (fli!) is not driven it goes to high level, VICII probably doesnt drive the address bus for the ghost byte, tho that would defeat some of the hardwrited behaviour. |
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Oswald
Registered: Apr 2002
Posts: 5031 |
@trident ah, then its the article by you I have thought of, never really wrapped around my head this but getting to finally understand it. great write up. |
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chatGPZ
Registered: Dec 2001
Posts: 11154 |
If it didn't drive the address bus, it'd either always fetch $3fff - or whatever address was on the bus in the previous access (more likely).
The $ff pattern in the FLI bug is also due to precharging, btw. |
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Oswald
Registered: Apr 2002
Posts: 5031 |
Quote: If it didn't drive the address bus, it'd either always fetch $3fff - or whatever address was on the bus in the previous access (more likely).
The $ff pattern in the FLI bug is also due to precharging, btw.
good points |
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chatGPZ
Registered: Dec 2001
Posts: 11154 |
What happens when the address bus is not driven you can see in the color of the FLI bug (well one of them) - its the value of the instruction that was fetched in the previous access. |
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Oswald
Registered: Apr 2002
Posts: 5031 |
Quote: What happens when the address bus is not driven you can see in the color of the FLI bug (well one of them) - its the value of the instruction that was fetched in the previous access.
but what explains that, hence VICII data bus being 12 bit wide, and 4 of those connected to d800 (color ram) directly afaik and not to memry where instr was read from? whats going on here? |
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chatGPZ
Registered: Dec 2001
Posts: 11154 |
When the bus is floating (ie not driven by anything) then whatever was on the bus before stays there for a small time, because of the parasitic capacitance of the bus itself.
In case of the FLI bug color what happens is basically:
1a) CPU puts address on the address bus
1b) RAM "answers" by butting data on the data bus
1c) CPU reads data from data bus
1d) bus goes inactive ("floating")
2a) VICII does NOT put an address on the address bus
2b) RAM does NOT answer anything either
2c) VICII DOES read data from the data bus, and sees the value from the CPU cycle
Oh and as for that "direct" connection - it's still a bus, the CPU can read/write to colorram by default, and thats why the value ends up there. |
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Oswald
Registered: Apr 2002
Posts: 5031 |
yeah but VIC reads 12 bits every cycle it steals from the cpu afaik on a badline, how come the color read comes from the instruction and not the "$ff" |
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chatGPZ
Registered: Dec 2001
Posts: 11154 |
That value is not even read from the databus, its the precharged value from the internal bus on the chip (Its in the 3 DMA setup cycles). |
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Oswald
Registered: Apr 2002
Posts: 5031 |
Quote: That value is not even read from the databus, its the precharged value from the internal bus on the chip (Its in the 3 DMA setup cycles).
VICII has 12 bit databus, why is 8 bits $ff and 4 bits from an opcode at the fli bug ? why dont it reads all 8 bits of opcode instead of $ff, and $0f for color ram ? |
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